A level shifter is conventionally used to change the logic level at the interface between two different semiconductor logic systems. For example, FIG. 1 of the drawings illustrates a level shifting interface 30 between a SRAM 32 and a sensing amplifier 34 that amplifies data read from the SRAM 32. As the differential voltage representing the data supplied from the SRAM is not large enough to support reliable operation of the sensing amplifier 34, the level shifter 30 is provided at the interface to translate a small voltage range of the SRAM into a larger voltage range required by the sensing amplifier. The level shifter 30 may comprise an input differential amplifier 36 supplied by the output voltage of the SRAM and an output stage 38 providing a signal that varies over a larger voltage range sufficient to support operation of the sensing amplifier. The output stage may be implemented, for example, by a pair of hold transistors that are coupled to the output of the differential amplifier 36 to provide latching the outputs of the shifter in the corresponding logic state in accordance with the voltage values at the inputs of the differential amplifier.
However, in a high-speed level shifter, transient variations of the input values that occur when the inputs change their logic states, could cause the output transistors to latch in the wrong state. Accordingly, erroneous data would be supplied to the sensing amplifier 34.
Hence, it would be desirable to keep the level shifter from latching in a wrong logic state, in order to increase the reliability of its operation.